Scan test apparatus for digital systems having dynamic random access memory
US4827476A · kind A · utility
66Cited by
6References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1987 |
| Grant date | May 2, 1989 |
| Priority date | — |
| Expiry date | Apr 16, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan test apparatus is constructed to scan test a digital system having a memory system containing dynamic random access memory (DRAM). The scan test apparatus is given access to the memory system so that test control signals can preset the refresh counter (for the DRAM) and initialize the memory for later testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.