Screenable power chip mosaics, a method for fabricating large power semiconductor chips
US4829014A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 2, 1988 |
| Grant date | May 9, 1989 |
| Priority date | — |
| Expiry date | May 2, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An additive process allowing discretionary interconnection of only the acceptable devices on a semiconductor wafer includes screen printing a polyimide layer over the wafer to form vias over all of the device contact pads on the wafer while coating the remainder of the wafer. The devices are then individually tested through the vias and, when a device is determined to be unacceptable according to predetermined specifications, the vias above that device are filled with polyimide. A layer of metal is next deposited over the entire wafer by evaporation and makes electrical contact with only the acceptable devices since the unacceptable devices have been blocked off. The metal layer is thereafter patterned to leave an interconnection pattern wherein only the acceptable devices on the wafer are electrically connected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.