Polysilicon pattern for a floating gate memory

US4829351A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Bruce E. Engles · Austin, US
• Gianfranco Gerosa · Austin, US

Key dates

• Filing date: Mar 16, 1987
• Grant date: May 9, 1989
• Expiry date: Mar 16, 2007

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10T428/12528

Abstract

An integrated circuit floating gate memory is formed using two layers of polysilicon. The first layer of polysilicon is patterned twice, once before the second polysilicon layer is deposited, and again as part of the etch of the second layer of polysilicon. Stringers of the second layer of polysilicon can form along the edge of the first etch of the first layer of polysilicon. The first etch of the first layer of polysilicon is patterned so that even if these stringers are subsequently formed, there is no harm.