Communication bit pattern detection circuit
US4829462A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1986 |
| Grant date | May 9, 1989 |
| Priority date | — |
| Expiry date | Jun 13, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A communication bit pattern detection circuit that provides an output signal upon the occurrence of one of several predefined bit patterns for a series of a specified number of bits for a multiple of input signals where each input signal is a continuous stream of serial bit data. The communication bit pattern detection circuit includes a detection stage having combinational logic connected to receive the input signals and providing the logically combined bits to latches of a shift register. The number of latches in the shift register is less than the specified number of bits for the predefined bit patterns. The output of these latches are provided to a logic stage that includes additional combinational logic that provides a nondetection signal. This nondetection signal is provided to indicate that the bits received are not part of any of the predefined bit patterns. The nondetection signal is input to reset a counter. The output of the counter is decoded to provide a signal when the counter counts to the specified number of bits in the predefined bit patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.