Semiconductor memory device
US4829477A · kind A · utility
4Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1987 |
| Grant date | May 9, 1989 |
| Priority date | — |
| Expiry date | Mar 5, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided with a clamp circuit for clamping a driving level of a write circuit so that the information on a bit line can be transmitted quickly to a data bus at the time of a read-out operation by using transistors having a low threshold value (or a large mutual conductance) for the transistors constituting a column transfer gate, and so that a write-in operation can be carried out at a high speed by using transistors having a large mutual conductance for driving transistors of the write circuit and setting a required level by clamping the driving level of the write circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.