Voltage limiting circuit
US4831323A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 1986 |
| Grant date | May 16, 1989 |
| Priority date | — |
| Expiry date | Dec 18, 2006 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G11/002
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A voltage limiting circuit with two-terminal network character is described which has a sharp-edged limitation characteristic curve and a short response time. According to the invention, this is achieved by means of two current mirror circuits connected to each other in a ring circuit, with a clamping transistor being at the same time a transistor of one of these current mirror circuits. A biasing current is fed from a current source into the remaining elements of the two current mirror circuits, this biasing current subjecting the semiconductor junctions of these current mirror elements to current and charging the diffusion and depletion layer capacitances thereof already prior to the limitation onset. The consequence thereof is a rapid limitation effect when the limit voltages are being reached. The effect achieved by means of a biasing voltage source between the two current mirror elements of the current mirror circuit containing the clamping transistor is that the input current received by the voltage limiting circuit in the non-limiting voltage range remains much smaller than the biasing current fed into the ring circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.