Circuit and method for page addressing read only memory
US4831522A · kind A · utility
30Cited by
7References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1987 |
| Grant date | May 16, 1989 |
| Priority date | — |
| Expiry date | Feb 17, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0623
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method for page addressing computer read-only memory (ROM) includes expanded ROM (12 and 13) and an address signal generator (20). Address signal generator (20) includes address line generator (21) for providing sufficient additional binary lines to expanded ROM (12 and 13) for addressing the entire expanded ROM memory space and a decoder circuit (22) for detecting the presence of prechosen addresses on the computer system address bus. The prechosen addresses permit selection of page increments in expanded ROM memory space for addressing over the more limited system address bus received by the original ROM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.