Digital multiplier architecture with triple array summation of partial products
US4831577A · kind A · utility
19Cited by
14References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1986 |
| Grant date | May 16, 1989 |
| Priority date | — |
| Expiry date | Sep 17, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention performs the multiplication and/or accumulation of digital numbers in either two's complement of unsigned magnitude representation. A modified Booth algorithm minimizes the number of partial products generated. Two adder arrays sum the partial products in parallel to generate intermediate values which are then summed by a third adder array. The partial products are divided between the two adder arrays in a manner which optimizes the speed of the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.