Method of fabricating a tapered via hole in polyimide
US4832788A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 1987 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | May 21, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/978
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a tapered via hole in a polyimide layer of an integrated circuit includes the steps of: disposing a layer of SiO.sub.2 on the polyimide layer and a layer of photoresist on the SiO.sub.2 such that the layers have an opening which exposes a region of the polyimide layer for the via hole; etching the exposed polyimide region partway through the polyimide layer, while simultaneously etching back the photoresist on the sidewalls of the opening to thereby uncover a strip of SiO.sub.2 adjacent to the perimeter of the exposed polyimide region; enlarging the exposed region of the polyimide by etching the uncovered strip of SiO.sub.2 ; and repeating the etching step and enlarging step a predetermined number of times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.