Fabrication of MOS-transistors

US4833097A · kind A · utility

Inventors

• Alan L. Butler · Eindhoven, NL
• Peter Childs · London, GB

Key dates

• Filing date: Apr 4, 1988
• Grant date: May 23, 1989
• Expiry date: Apr 4, 2008

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

A process for the fabrication of shallow p.sup.+ and n.sup.+ doped layers suitable for the sources and drains of submicron CMOS transistors comprises applying a layer of polysilicon (1) over a gate oxide layer (2) which is surrounded by a field oxide isolation layer (3) located on a suitable substrate (4) and applying a resist layer (5) to the polysilicon layer in a selected region of the polysilicon layer overlying the gate oxide to define a gate electrode. Selective ion implantation then takes place to form the source and drain regions (6, 7), the implementation extending through the oxide layer to a limited extent except in the region masked by the resist layer. The polysilicon layer and resist layer are then etched away to leave a gate electrode (8) extending from the oxide layer (2) and the source and drain regions are then activated and difussed to .about.0.1 .mu.m junction depth. The oxide is then removed in said source and drain regions and a silicide or other conductive layer (10) is then applied to reduce the sheet resistance to .about.8.OMEGA./ or less.