Sample/hold amplifier for integrated circuits
US4833345A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 3, 1988 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | Feb 3, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sample/hold amplifier comprising two transconductance stages with their inverting input terminals connected together. In sample mode, the input signal is connected to the non-inverting input of the first stage, and a hold capacitor is connected to the non-inverting input terminal of the second stage and driven by the amplifier output through a feedback circuit which forces the hold capacitor voltage to track the input signal. Upon switchover to hold mold, the roles of the two transconductance stages are interchanged: The non-inverting input terminal of the first stage is connected through a feedback circuit to the amplifier output, and the second stage receives as an input signal the voltage of the hold capacitor, which now is disconnected from the amplifier output. The net offset voltage developed on the hold capacitor is the difference between the respective offsets of the two transconductance stages. This net offset voltage is compensated for by an equal and opposite voltage in hold mode, due to the interchange of roles of the two transconductance stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.