Charge disturbance resistant logic circuits utilizing true and complement input control circuits
US4833347A · kind A · utility
14Cited by
6References
58Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 12, 1988 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | Jan 12, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0948
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A cross-coupled load logic gate family which will keep voltage at a logic gate output below that of a switching threshold and a subsequent logic gate during a charge disturbance upset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.