Programmable logic and driver circuits
US4833349A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 1987 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | Sep 1, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17712
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An output driver circuit is described which can be programmed by the user into tri-state or open-collector configurations, depending on the needs of the user. The driver circuit comprises a pair of a first pull-up and a pull-down FET transistor. The source of the pull-up transistor and drain of the pull-down transistor are both connected to the output of the driver. The gates of the pair of transistors are controlled by an input signal and its complement. The driver further includes a second pull-up FET whose source is connected to the output of the driver. The channel width to channel length ratio of the second pull-up transistor is at least about an order of magnitude greater than that of the first pull-up transistor. The driver further includes a control means responsive to the input signal for applying a second signal to the gate of the second pull-up transistor for programming the driver into tri-state or open-collector modes. The driver circuit may be controlled by the output of an OR gate in an AND-OR array in a FPLA or device. The driver is programmable by programming the AND gate or OR gate array and applying selected input signals to the AND gate array; the driver can als…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.