Analog macro embedded in a digital gate array
US4833425A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1988 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | Mar 25, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.