Semiconductor device with a wiring layer having good step coverage for contact holes
US4833519A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 1987 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | May 15, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76849
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are disclosed for improving step coverage of a wiring layer of a semiconductor device especially at the contact holes thereof. The inside of the contact holes are covered by a polysilicon layer deposited by chemical vapor deposition (CVD), and selectively doped with impurities having the same conductivity type as the contact region which the polysilicon layer contacts at the bottom of the contact hole. The remaining part of the contact hole is buried with SiO.sub.2, and the wiring layer is formed on it. Since the step coverage of the material deposited by CVD is very good, the disconnection at the side walls of the contact hole is avoided. Further, short circuits caused by growth of spikes of eutectic of silicon and aluminum is also avoided. If the surface of the polysilicon layer is covered with a thin film of SiO.sub.2 or Si.sub.3 N.sub.4, the material to bury the contact hole may be replaced by other materials such as polysilicon or amorphous silicon. Further, a barrier layer may be provided between the wiring layer and the polysilicon layer. This prevents the migration of aluminum over the polysilicon, so that the reliability of the wiring is further impr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.