Logical arrangement for controlling use of different system displays by main processor and co-processor
US4833596A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 1988 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | Mar 23, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/04
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and system for controlling the display of data in a data processing system that includes a main processor, a memory subsystem, and an Input/Output subsystem which includes an I/O Channel Controller for managing traffic on an I/O bus having an attached co-processor and a plurality of I/O devices including display devices with different reserved I/O address space. The main processor can establish different display modes for displays having different reserved I/O address space, which generally indicates different display types. In one mode, a display is assigned exclusively to the main processor and attempted data transfers by the co-processor to that display are suppressed. In a second mode, a display is time-shared between processors by establishing a virtual video buffer in main memory which is written into by one processor when the other processor has control of the display device. The contents of the virtual and real buffer are swapped whenever the display is reassigned to the other processor. In the third mode, co-processor data in the virtual buffer can be "windowed" onto the display device when it is assigned to the main processor. In the fourth mode, a display assign…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.