I/O interrupt handling mechanism in a multiprocessor system
US4833598A · kind A · utility
20Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1987 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | Jul 21, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor system in which a plurality of instruction processors (IP's) share a main storage (MS) and a channel controller (CHC) through a system controller (SC), when an I/O interrupt request is issued, IP's connected to the SC are examined to determine whether each of the IP's is executing an instruction which permits acceptance of the I/O interrupt request during the execution of the instruction. If one of the IP's is not executing such an instruction and can accept the I/O interrupt request, that IP will be selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.