FIFO memory with decreased fall-through delay
US4833655A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1985 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | Jun 28, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first-in, first out data memory minimizes fall-through delay. The FIFO memory has a plurality of cascaded register stages arranged in sections, with the input of each section selectively coupled to a bypass bus. Data is introduced on the bypass bus, and control logic writes the data into the section nearest the output which is currently not full. The individual register stages are self-clocked, so that data is then shifted toward the output through any vacant registers. In another aspect, the register stages are arranged in sections of different length, with the shortes section closest to the output and the longest section closest to the input. Decreased fall-through delay is achieved by minimizing the length of the FIFO buffer actually traversed by the data while insuring that the order of the data remains unchanged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.