Hard-wired serial Galois field decoder
US4833678A · kind A · utility
32Cited by
1References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 22, 1987 |
| Grant date | May 23, 1989 |
| Priority date | — |
| Expiry date | Jul 22, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/724
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error detection and correction processor computes in real time successive approximations to a Galois field error locator polynomial and a Galois field error evaluator polynomial from the remainder or syndrome polynomial of a received block of data by executing successive iterations of a recursive algorithm. The processor stores each coefficient of the polynomials in an individually addressable memory location. During each iteration, the processor operates on successive ones of the coefficients of each polynomial in successive memory access cycles to compute a new version of the coefficient which replaces the old one in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.