Method of fabricating self-aligned zener diode
US4835111A · kind A · utility
8Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1987 |
| Grant date | May 30, 1989 |
| Priority date | — |
| Expiry date | Nov 24, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/983
Abstract
A method of fabricating a self-aligned zener diode provides for N.sup.+ and P.sup.+ regions having the large dopant concentrations necessary for compatibility with shallow junction silicon gate CMOS devices. A contact region is provided on the substrate, doped with N-type dopant ions, and etched to cover a portion of the region in which a zener diode is to be formed. A P.sup.+ region is implanted using the doped contact region as a mask. Then, N-type dopant ions are diffused from the contact region to the underlying substrate, thereby providing self-aligned P.sup.+ and N.sup.+ regions having a well defined P-N junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.