Arbiter circuits with metastable free outputs
US4835422A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 1988 |
| Grant date | May 30, 1989 |
| Priority date | — |
| Expiry date | Mar 14, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed low-power-consumption two-input arbiter circuit comprises two input inverters, two inverters cross-coupled to form a latch and two additional inverters that drive a difference detector. The detector responds only to a voltage difference on its inputs that exceeds a specified value. In this way, signals are blocked from appearing at the outputs of the detector while the latch is in a metastable state. Additionally, an n-input arbiter circuit comprises (n-1)+(n-2)+ . . . +[n-(n-1)] two-input arbiter circuits and logic circuitry connected to the outputs of the two-input circuits for supplying a priority signal to one and only one at a time of n output terminals of the n-input circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.