ESD protection circuit employing channel depletion
US4835653A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1988 |
| Grant date | May 30, 1989 |
| Priority date | — |
| Expiry date | Jan 19, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
Abstract
An electrostatic discharge protection circuit includes a P.sup.- doped channel and an N.sup.- doped channel that form a serial path between a signal pad and a transistor. Holes are depleted from the P.sup.- doped channel in response to a negative electrostatic discharge on the input signal pad; and electrons are depleted from the N.sup.- doped channel in response to a positive electrostatic discharge on the input signal pad. When either depletion occurs, the path from the signal pad to its transistor is open circuited; and so the transistor is protected. Conversely, when no electrostatic charge exists on the signal pad, the path through the P.sup.- doped channel and the N.sup.- doped channel is highly conductive; and so signals pass between the pad and the transistor very quickly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.