Multiplexer/demultiplexer circuitry for LSI implementation
US4835770A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1987 |
| Grant date | May 30, 1989 |
| Priority date | — |
| Expiry date | Sep 28, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q11/06
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A multiplexer/demultiplexer comprises a code pattern generator for generating a series of unique code patterns at periodic intervals, a plurality of multiplexers cascaded from the code pattern generator to one end of a channel. Each of the multiplexers includes a synchronizer for detecting a particular one of the unique code patterns and a slot selector for multiplexing input data packets into time slots uniquely identified by the particular code pattern to form a data bit stream with the code patterns which is forwarded to the channel. A plurality of demultiplexers are connected to the opposite end of the channel, each of the demultiplexers comprising a synchronizer for detecting a particular one of the code patterns from the data bit stream and a gate for extracting data packets from the time slots uniquely identified by the detected code pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.