CMOS reference voltage generation
US4837459A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 1987 |
| Grant date | Jun 6, 1989 |
| Priority date | — |
| Expiry date | Jul 13, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/245
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A process insensitive reference voltage generator includes a first and second identical FET devices coupled in a parallel configuration with a first biasing network, of FET devices, interconnecting the substrate terminal of the first FET device to a first node formed between a positive voltage supply and ground potential. The control terminal is connected to a second node whose voltage potential is different from that of the first node. The substrate terminal of the second FET device is connected to the source terminal. The source terminals of both FET devices are connected to the respective input terminals of an operational amplifier whose output is connected to the control terminal of said second FET device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.