Complementary MOS circuit having decreased parasitic capacitance
US4837460A · kind A · utility
44Cited by
7References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 23, 1984 |
| Grant date | Jun 6, 1989 |
| Priority date | — |
| Expiry date | Jan 23, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/213
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The substrate voltages V.sub.1 and V.sub.2 of NMOS and PMOS transistors, respectively, which constitute a CMOS circuit and the source voltages V.sub.3 and V.sub.4 of these transistors have the following relationship: EQU V.sub.1 <V.sub.3 <V.sub.4 <V.sub.2 (where V.sub.1 may be equal to V.sub.3 or V.sub.4 may be equal to V.sub.2). In order to maintain the above relationship, it is preferable that internal power supply means are formed on the substrate upon which is also formed the CMOS circuit so that some of the above voltages may be produced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.