Phase locked loop clock synchronizer and signal detector
US4837781A · kind A · utility
20Cited by
3References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 7, 1987 |
| Grant date | Jun 6, 1989 |
| Priority date | — |
| Expiry date | Apr 7, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0087
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A phase locked loop system is described for synchronizaing a clock signal to an incoming digital signal and simultaneously detecting that digital signal. The loop is capable of unaided frequency acquisition, hence eliminating the need for special circuits to "pull" the loop into lock when the incoming data rate differs from the initial frequency of the VCO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.