Data transfer system and method of operation thereof
US4837785A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 14, 1983 |
| Grant date | Jun 6, 1989 |
| Priority date | — |
| Expiry date | Jun 14, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data transfer system with improved data transfer efficiency is provided. The system consists of a data interchange bus having two data transfer signal paths, an address signal path, and a plurality of control signal paths. Data interchange adapters and memory interchange adapters are coupled to the bus for transferring data thereover. A data interchange adapter transfers data on the first data signal path to another data interchange adapter or to a memory interchange adapter for storage in a memory device. A memory interchange adapter transfers data obtained from a memory device on the second data signal path to a data interchange adapter. Data transfers on the two data signal paths may be made simultaneously. Data transfers on both data signal paths are made synchronously. When an interchange adapter has data to be transferred, it provides an access request signal to a data interchange bus controller which intermittently latches all outstanding access requests, examines them, and produces a sequence of grant signals, each satisfying one of the latched request signals. When the sequence is completed, the controller again latches the access requests which had been raised during th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.