Method of fabricating MOS field effect transistor
US4838993A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1987 |
| Grant date | Jun 13, 1989 |
| Priority date | — |
| Expiry date | Dec 3, 2007 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/05
Abstract
A novel MOS field effect transistor which operates at high speed and with low power consumption has impurity doped source and drain regions deposited at 850.degree. C. or less by molecular layer epitaxial growth method. The molecular layer epitaxial growth is concurrently carried out with the control of impurity doping concentration so that the layers epitaxially deposited has a lightly doped region and a heavily doped region. Since the thickness of the growth layer can be controlled with a degree of accuracy on the order of an atom layer and thermal diffusions can remarkably be reduced by the low deposition temperature, an overlap of a gate over each of the source and drain regions can be reduced to 500 .ANG. or less.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.