Analog-to-digital conversion
US4839650A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1988 |
| Grant date | Jun 13, 1989 |
| Priority date | — |
| Expiry date | Jun 8, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Analog-to-digital converters are subject to errors including the known half least significant bit quantization error and also bit weighting errors due to lack of an ideal binary relationship between the transition points of all the bits. The known statistical average error reduction method in which a relatively small dither component is added to the analog input signal can only fractionally reduce overall error and has little effect on bit weighting errors. Herein the analog signal is added to a dither signal, for example a ramp signal, which varies through half the peak to peak digitization range of the converter so that irrespective of the input signal all output signal bits, other than the most significant bit, are "on" for one half of the sampling period. The result is that all the less significant bit errors are cancelled leaving only the easily compensated most significant bit error. A random component can be added to the dither signal to reduce the quantization error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.