Static frame digital memory
US4839796A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1987 |
| Grant date | Jun 13, 1989 |
| Priority date | — |
| Expiry date | Jul 16, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital memory system wherein a plurality of frames in the memory, each frame holding a page of data, may be rapidly accessed utilizing static column dynamic random access memories (SCRAMs). The SCRAM devices are configured such that a page of data is located on corresponding rows of a plurality of SCRAM devices, the corresponding rows being referred to as frames. Once a row has been activated into static column mode, successive accesses to the same row may be made very rapidly. In the presently preferred embodiments, a plurality of banks are provided, each bank being capable of holding one page of data in static column mode. In the preferred embodiments, a tag register and comparator are provided which are associated with each bank. The tag register contains a portion of the address which previously caused an access to its corresponding bank. An address is presented to all the tag registers and comparators. If a match occurs, a memory access to the bank corresponding to the matching tag register may be made while the row in the selected bank is still in static column mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.