Apparatus for performing floating point arithmetic operations and rounding the result thereof
US4839846A · kind A · utility
56Cited by
8References
10Claims
0Family size
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Key dates
| Filing date | Mar 12, 1986 |
| Grant date | Jun 13, 1989 |
| Priority date | — |
| Expiry date | Mar 12, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49957
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation unit capable of performing round processing at a high speed in a floating point operation. A circuit for detecting an overflow on the condition of a signal representing all 1's in an output of a mantissa shifter and a signal representing round-up, a carry look-ahead circuit and a circuit for generating a round precision signal are provided. When the overflow takes place, the mantissa is produced as "1". The operation unit is compatible to single, double and extended precisions recommended by Institute of Electrical and Electronic Engineers (IEEE).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.