Memory cell circuit
US4839863A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 1987 |
| Grant date | Jun 13, 1989 |
| Priority date | — |
| Expiry date | Sep 28, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory cell circuit has a pair of transistors in which the gates are connected to the drains, a first and a second access transistor whose gates are connected to a read line and which are located between gate-drain connection of said pair of transistors and a pair of bit lines. The memory cell circuit also includes a third access transistor whose gate is connected to the read line and is located in the circuit between said first access transistor and the gate of said pair of transistors corresponding to the first access transistor, and a fourth access transistor whose gate is connected to the read line and is located in the circuit between said second access transistor and the gate of said pair of transistors corresponding to the second access transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.