Fast remainder decoding for a Reed-Solomon code
US4839896A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1987 |
| Grant date | Jun 13, 1989 |
| Priority date | — |
| Expiry date | Feb 10, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/151
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods are disclosed for providing fast decoding of Reed-Solomon and related codes. Cases of one and two data symbol errors are decoded directly from the remainder using a large pre-computed table without calculating syndromes. Techniques for decoding cases of more than two errors are given where an optimized Chien search is used when more than four errors remain; when four or fewer errors remain, the Chien search is eliminated in favor of locating an error by direct solution of the error locator polynomial. The error locator and syndrome polynomials are adjusted after each error is found, and the error evaluator polynomial need not be computed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.