Three-dimensional microelectronic package for semiconductor chips
US4841355A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 10, 1988 |
| Grant date | Jun 20, 1989 |
| Priority date | — |
| Expiry date | Feb 10, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1627
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional microelectronic package for semiconductor chips includes a plurality of cavity wafers, each cavity wafer having a plurality of cavities and tunnels for providing coolant to the cavities, and a plurality of wafer packs provided between adjacent, stacked cavity wafers, each cavity wafer and wafer pack having conductive paths. Chip carriers for housing semiconductor chips are attached to portions of the wafer packs corresponding to the positions of the cavities in the cavity wafers. The chip carriers electrically interconnect the semiconductor chips with the connective paths of the wafer packs, and, through the wafer packs, the cavity wafers. The chip carriers also provide a medium for exchanging heat between the semiconductor chips and the coolant flowing to the cavities in the cavity wafers. Conductive paths provided in the cavity wafers electrically interconnect the various wafer packs. The application of pressure along the z-axis of the package creates liquid-tight seals between the chip carrier packages and the cavity wafers and establishes the electrical interconnections between the cavity wafers and the wafer packs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.