System architecture for a test apparatus having primary and dependent processors
US4841437A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 1985 |
| Grant date | Jun 20, 1989 |
| Priority date | — |
| Expiry date | Sep 18, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multifunction test apparatus which is capable of performing total communication network measurments and includes a primary processor linked to a number of dependent processors. The primary processor plays a number of different roles in the functioning of the test system, which roles require substantial interaction between the primary processor and dependent processors. In some test configurations, the primary processor becomes a dependent processor. In other configurations, the primary processor is timeplexed and interleaved with the operation of the dependent processors in performing subfunctions for the dependent processors. The architecture also provides for direct communication and resource sharing between the dependent processors. In another aspect of the subject invention, the primary processor performs overflow calculations for the dependent processors. Finally, the device is arranged such that all test functions are displayed with consistent screen formats.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.