Architecture to implement floating point multiply/accumulate operations
US4841467A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1987 |
| Grant date | Jun 20, 1989 |
| Priority date | — |
| Expiry date | Oct 5, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiply/accumulator chip architecture capable of operating at a 20 megahertz system clock rate is designed so as to accept floating point numbers in sign magnitude form, to compute a product of the fractional portions thereof and to convert the fractional result into two's complement form for accumulation with the results of a previous product. This architecture readily permits the computation of vector-type inner product operations in a high speed pipelined fashion. Additionally, leading zero's and leadings one's detection is carried out in a multiply parallel fashion so as to rapidly produce post normalization results from the additive portion of the system. The system is implementable on a single integrated circuit chip in which an array multiplier is present so as to minimize inter-chip delays. The architecture of the present invention provides a high speed floating point multiply and accumulate operation with a short pipeline latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.