Extended floating point operations supporting emulation of source instruction execution
US4841476A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 1986 |
| Grant date | Jun 20, 1989 |
| Priority date | — |
| Expiry date | Oct 6, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a system which emulates execution of source CPU instructions and includes a translating unit (translator) for converting source instructions to target instructions and a target CPU instruction unit for processing and issuing translated target instructions, provision is made for accelerating instruction, translation, issue, and execution when certain source floating point arithmetic instructions are emulated for execution. When a source floating point arithmetic instruction is emulated, a token is placed in a wait queue in the translator to prevent the translation of any source instructions and issue of any target instructions until condition and interrupt information is available and validated. In addition, emulation of source RX-type floating point instructions is enhanced by provision of registers in the instruction unit which receive X-field denoted operands, and which thereby permit a target CPU execution unit to perform the emulation by conducting register-to-register operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.