Cross-tie memory system
US4841480A · kind A · utility
4Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1987 |
| Grant date | Jun 20, 1989 |
| Priority date | — |
| Expiry date | Oct 9, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/0866
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Double complementary storage is provided for a single binary digit in a quad store cross-tie memory. A correlated double sampling signal processing system is used to increase data signal level and facilitate discrimination in cross-tie memories. A method is also provided for accomplishing write and read functions in a quad store cross-tie memory using only a single pulse for either function. A set of four memory elements, arranged in two row-aligned complementary pairs, stores a single data bit, and is under four column conductors for reading data, two row conductors, and a write conductor for writing data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.