Dynamic sense amplifier for CMOS static RAM
US4843264A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 1987 |
| Grant date | Jun 27, 1989 |
| Priority date | — |
| Expiry date | Nov 25, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35613
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A sense amplifier for use in a CMOS static random access memory. The core of the sense amplifier comprises seven transistors: two sensing transistors with their sources coupled to a common pull down node, a pull down transistor for drawing current from the pull down node during sensing operations, and a four transistor latch coupled to the drains of the two sensing transistors. The four transistor latch comprises two cross coupled CMOS inverters. When the pull down transistor is activated, the four transistor latch automatically amplifies the voltage differential on the gates of the two sensing transistors, typically latching in less than two nanoseconds. Since the latch is made up of CMOS inverters, no d.c. current is drawn by the sense amplifier after the input data has been sensed and latched. As a result, relatively powerful transistors can be used in the sense amplifier. The use of powerful transistors to produce differential output signals significantly reduces the amount of circuitry needed in the output driver of the memory device incorporating this sense amplifier. Furthermore, this sense amplifier significantly improves the access time of a memory device by enabling sensi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.