Oversampled A/D converter having digital error correction
US4843390A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 1988 |
| Grant date | Jun 27, 1989 |
| Priority date | — |
| Expiry date | Feb 24, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/418
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An oversampled A/D converter which utilizes digital error correction is provided. In one form, the present invention is used with a sigma delta modulator having a plurality of rank ordered quantization loops, Each quantization loop contains an analog integrator circuit of predetermined gain which is subject to variation, thereby introducing errors. When the product of a reciprocal of the analog integrator gain and the gain of a digital gain stage of a subsequent quantization loop equals one, minimum noise exists in the data conversion. A digital gain control circuit is coupled to the digital gain stage for adjusting the gain of the digital gain stage during a calibration mode to provide minimum noise in the converter, thereby compensating for errors attributable to the analog integrator circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.