Virtual memory cache for use in multi-processing systems
US4843542A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1986 |
| Grant date | Jun 27, 1989 |
| Priority date | — |
| Expiry date | Nov 12, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for maintaining data consistency among distributed processors, each having its associated cache memory. A processor addresses data in its cache by specifying the virtual address. The cache will search its cells for the data associatively. Each cell has a virtual address, a real address, flags and a plurality of associated data words. If there is no hit on the virtual address supplied by the processor, a map processor supplies the equivalent real address which the cache uses to access the data from another cache if one has it, or else from real memory. When a processor writes into a data word in the cache, the cache will update all other caches that share the data before allowing the write to the local cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.