Multiple error trapping
US4843607A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 1987 |
| Grant date | Jun 27, 1989 |
| Priority date | — |
| Expiry date | Dec 17, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/17
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
By translating in accordance with a predetermined permutation the virtual check locations of a virtual message re-encoder, plural erroneous symbols (up to a certain limit) occurring in any pattern in a received codeword may be trapped simultaneously in virtual check locations. By simply adding to them the corresponding virtual check symbols computed by the virtual message re-encoder, the correct codeword is easily obtained. In one embodiment of the invention, any pattern of two erroneous symbols in a codeword of length n may be trapped in this manner by defining the predetermined permutation in accordance with a modulus n cyclic difference set. In this embodiment, for an RS(31, 25) code, the cyclic difference set (0, 4, 10, 23, 24, 26) may be used as the predetermined permutation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.