High-speed dual mode graphics memory
US4845640A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1987 |
| Grant date | Jul 4, 1989 |
| Priority date | — |
| Expiry date | Mar 11, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/127
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A high-speed graphics memory providing line mode and area mode data transfer at high speeds comprises a frame buffer structure, with unique address alignment and corresponding data manipulation to provide line mode and area mode pixel data transfer of comparable time intervals. The frame buffer comprises independently addressable 16 byte-wide video memories. The 16 memories provide a 128-bit contiguous horizontal pixel sequence in the line mode, and provide a two-dimensionally contiguous array of pixels comprising 8 bits by 2 bytes when in the area mode, from which an 8.times.8 bit area is selected at any address location in the entire image bit map. The pixels included in a particular line mode or area mode data transfer are directly addressable by external equipment, such as graphics processors, to provide a high-speed graphic display system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.