Image processor with free flow pipeline bus
US4845663A · kind A · utility
18Cited by
18References
47Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1987 |
| Grant date | Jul 4, 1989 |
| Priority date | — |
| Expiry date | Sep 3, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital image processing system has a pipeline bus for transferring addresses and data in parallel among the components of the system, which include an image memory, an address generator and an intensity processor. The pipeline bus includes a pipeline address bus, a pipeline data bus, and a master timing bus. Through the use of handshake signals, the pipeline bus permits a free flow of pipelined data among the components at whatever rate is necessary to complete the particular processing task. Image data is transferred in the form of N.times.N pixel subimage blocks which can be addressed using a single address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.