On-chip bit reordering structure
US4845664A · kind A · utility
144Cited by
9References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1986 |
| Grant date | Jul 4, 1989 |
| Priority date | — |
| Expiry date | Sep 15, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method whereby a static column mode DRAM can access a unique data bit located anywhere within the array chip and sustain a continuous transfer of requested bits in a contiguous group of bits (i.e. block). Steering of the data in a prescribed order is accomplished via a special steering and gating network. A control line, toggle, is used on both rising and falling edges to produce this gapless transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.