Divider circuit
US4845727A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 19, 1987 |
| Grant date | Jul 4, 1989 |
| Priority date | — |
| Expiry date | Nov 19, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/542
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pulse train divider circuit includes a first flip-flop (1) whose Q output is connected to the D input of a second flip-flop (2) whose Q output is connected to the D input of the first flip-flop (1). A pulse train to be divided is applied via an input (3) directly to the clock input C of the first flip-flop (1) and via a circuit (4) which delays the pulse train applied to the clock input C of the flip-flop (2) to provide a given phase relationship between the pulse trains at the two clock inputs. The circuit divides-by-two, and the resulting divided pulse trains available at the various outputs have phase relationships depending on the phase relationship of the applied pulse trains at the clock inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.