Programmable logic device
US4847612A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 13, 1988 |
| Grant date | Jul 11, 1989 |
| Priority date | — |
| Expiry date | Jan 13, 2008 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q3/521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input pins can be programmably connected to any input of any functional unit, and the outputs of functional units can be programmably connected to any input of any functional unit or any output pin. The interconnection matrices may be a simple array of crossing conductive lines with crossings connected by fuses, EPROM, or EEPROM switches or may have additional series switches to limit the effective impedance so as to speed propagation through these matrices. A fast path through one functional unit bypassing the interconnection matrices is available for a limited number of input and output pins. Multiplexers and other structures may be provided at ends of the fixed conductive lines to enable exhaustive testing of individual functional units, interconnections and logic, and structure may also be provided for on-chip monitoring of state information and providing the information to the external w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.