Main memory access in a microprocessor system with a cache memory
US4847758A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1987 |
| Grant date | Jul 11, 1989 |
| Priority date | — |
| Expiry date | Oct 30, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a high speed buffer, or cache, memory for temporarily storing recently executed instructions and a slower main memory in which is stored the system's operating program. Rather than sequentially accessing the cache memory to determine if the next instruction is stored therein and then accessing the main memory if the cache memory does not have the next instruction, system operating speed is increased by simultaneously accessing the cache and main memories. By accessing the main memory during its row address strobe (RAS) precharge time while simultaneously accessing the cache memory, the time necessary for the system's processor unit (PU) to read the next instruction from the main memory when not stored in the cache memory is substantially reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.