Input register for test operand generation
US4847800A · kind A · utility
12Cited by
5References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 23, 1987 |
| Grant date | Jul 11, 1989 |
| Priority date | — |
| Expiry date | Oct 23, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/583
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Sequential faults are not tested for adequately when using test input operands generated in the chip from a random number generator to test the logic circuits in a very large scale integrated (VLSI) chip. Accordingly this application teaches the efficient construction of a test operand generator, using an input register with properly randomized feedback to break up sequential patterns which would otherwise develop in the input register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.