Compact galois field multiplier
US4847801A · kind A · utility
41Cited by
2References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 26, 1987 |
| Grant date | Jul 11, 1989 |
| Priority date | — |
| Expiry date | Oct 26, 2007 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/158
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Multiplication of two mq-bit bytes (in GF2.sup.mq) is reduced modulus an irreducible polynomial in GF2.sup.m of degree q to multiplication among two sets of q m bit bytes (in GF2.sup.m) in order to simplify hardware and reduce costs, by distributing the computation among a small number of programmable read only memories (PROMs) and adders.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.